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Tenbric/Research
Research Programme

Compute that
operates independently.

A proprietary low-power signal-compute architecture — validated across real hardware telemetry and network data — designed to monitor complex systems from an external layer and surface early transitions conventional monitoring often misses.


What it is

Digital systems often degrade in ways standard monitoring does not reliably capture. A GPU drifting before errors become visible. A network whose structure is weakening long before the event is obvious. A processor accumulating damage that threshold checks fail to separate from normal variation.

The common problem is that conventional monitoring is often too close to the system behaviour it is trying to interpret. When the signal is subtle, thresholding is late. When the dynamics are complex, simple alerts miss progression.

The TCF programme addresses this differently. It uses a proprietary external compute layer designed to learn normal system behaviour and surface meaningful deviation early, without depending on labelled failure examples. The aim is not just to flag anomalies, but to detect transition before conventional monitoring would typically act.

The underlying signal logic has been validated in software across two independent domains. The current research programme is focused on translating that validated software behaviour into low-power hardware suitable for edge, satellite, and body-worn deployment.


Validated results
+368%
vs best-tuned benchmark
GPU health monitoring
Validated on production hardware. No large labelled failure dataset required.
0.742
AUROC — hardware
failure triage
Validated on real failure events at production scale. No large labelled failure dataset required.
100%
accuracy — structural
collapse detection
Zero errors on every confident call. When the system is uncertain, it says so.
<1mW
target power —
hardware demonstrator
Coefficient package specified for low-power implementation work.
Applications

The same core signal logic has produced validated results across hardware telemetry and network data, supporting multiple application paths from a shared research base.

Active · Hardware demonstrator stage
GPU & AI
Hardware Monitoring
+368%
vs best-tuned benchmark
Continuous inference of GPU health state from raw telemetry. Designed to surface thermal, power, and behavioural drift earlier than threshold-led monitoring. No large labelled failure dataset required. Target: data centres, AI infrastructure, and constrained compute environments.
Active · Software deployed
Network Transition
Detection
100%
on every confident call, zero errors
Multi-class classification of structural transitions — distinguishing critical collapse from routine events, slow institutional decay from seasonal patterns. When the classifier is confident, it is correct. When it is not, it says so. Early warning signal detectable months before visible collapse events.
Research stage · Road map
Edge & Body-Worn
Sensing
~1pJ
target — ultra-low-power operation
The same research direction may support low-power sensing applications in environments where continuous digital pipelines are impractical. This includes constrained edge and physiological monitoring contexts where power budget and form factor matter.

Research stage

The software validation is complete. The coefficient package is specified for hardware implementation work. The current research programme is focused on hardware characterisation and practical deployment constraints.

The programme is structured around binary-outcome experiments. Each experiment either confirms a material's suitability for a specific computational role, or documents why it does not — both outcomes advance the design process.

We have submitted a funding application to a UK research programme and are in discussions with academic partners for formal computational characterisation. We are not yet in a position to name either.

If you are working in analog hardware, thin-film materials characterisation, or physical computing and are interested in the research direction, we welcome the conversation.


Intellectual property

The TCF architecture and its applications are protected by UK patent applications covering the compute framework, monitoring approach, and deployment-specific implementations.

The software framework is deployable today on digital hardware. The hardware programme is aimed at low-power embedded inference for environments where power, latency, or deployment constraints limit conventional digital pipelines.

18
UK patent applications
filed
2026
Hardware demonstrator
target

Hardware demonstrator in preparation.

The software validation is complete. The hardware programme is underway. If you are working in analog hardware, physical computing, or AI infrastructure and want to understand the direction of the research — get in touch.

Get in touch Industrial Signals
kieran@tenbric.com
Tenbric
TENBRIC Ltd | Registered in England and Wales
Company No. 16908826
1097a Manchester Road, Slaithwaite, HD7 5LU
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